C8051F121-GQR

Product Summary

The C8051F121-GQR is a Mixed Signal ISP Flash MCU. With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F121-GQR is truly stand-alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and configured by user firmware. The C8051F121-GQR can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware.On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug system supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using JTAG.

Parametrics

C8051F121-GQR absolute maximum ratings: (1)Ambient temperature under bias: -55 to 125 °C; (2)Storage Temperature -65 to 150 °C; (3)Voltage on any Pin (except VDD and Port I/O) with respect to DGND: -0.3 VDD +0.3V; (4)Voltage on any Port I/O Pin or /RST with respect to DGND: -0.3 to 5.8 V; (5)Voltage on VDD with respect to DGND: -0.3 to 4.2 V; (6)Maximum Total current through VDD, AV+, DGND, and AGND: 800 mA; (7)Maximum output current sunk by any Port pin: 100 mA; (8)Maximum output current sunk by any other I/O pin: 50 mA; (9)Maximum output current sourced by any Port pin: 100 mA; (10)Maximum output current sourced by any other I/O pin: 50 mA.

Features

C8051F121-GQR features: (1)High-Speed pipelined 8051-compatible CIP-51 microcontroller core (100 MIPS or 50 MIPS); (2)In-system, full-speed, non-intrusive debug interface (on-chip); (3)True 12 or 10-bit 100 ksps ADC with PGA and 8-channel analog multiplexer; (4)True 8-bit 500 ksps ADC with PGA and 8-channel analog multiplexer (C8051F12x Family); (5)Two 12-bit DACs with programmable update scheduling(C8051F12x Family); (6)2-cycle 16 by 16 Multiply and Accumulate Engine (C8051F120/1/2/3 and C8051F130/1/2/3); (7)128k bytes or 64k bytes of in-system programmable FLASH memory; (8)8448 (8k + 256) bytes of on-chip RAM; (9)External Data Memory Interface with 64k byte address space; (10)SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware; (11)Five general purpose 16-bit Timers; (12)Programmable Counter/Timer Array with 6 capture/compare modules; (13)On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor.

Diagrams